There are many integrated circuits (IC) chip, or die, packaging technologies. Many advanced IC packages minimize package thickness or “z-height” and/or integrate a plurality of chips. In some applications (e.g., mobile devices), package thickness is one of the most important parameters in response to the design trend toward thinner devices. To include more features and/or spare printed circuit board (PCB) area, packaged chips may be stacked (e.g., package-on-package, or “PoP” technology). Such stacked package architectures are generally contrary to reductions in package height, and so techniques to minimize the package z-height that are compatible with package stacking technologies are all the more advantageous.